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core8051s v2.4 handbook
actel corporation, mountain view, ca 94043 ? 2010 actel corporation. all rights reserved. printed in the united states of america part number: 50200084-2 release: september 2010 no part of this document may be copied or reproduced in any form or by any means without prior written consent of actel. actel makes no warranties with respect to this documentati on and disclaims any implied warranties of merchantability or fitness for a particular purpose. information in this doc ument is subject to change without notice. actel assumes no responsibility for any errors that may appear in this document. this document contains confidential proprietary informati on that is not to be disclosed to any unauthorized person without prior written cons ent of actel corporation. trademarks actel, actel fusion, igloo, libero, pigeon point, proasic, smartfusion and the associated logos are trademarks or registered trademarks of actel corporatio n. all other trademarks and service marks are the property of their respective owners.
core8051s v2.4 handbook revision 2 3 table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 utilization and performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 core8051s overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 supported interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 interface descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 tool flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 smartdesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 example system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 synthesis in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 place-and-route in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 core8051s features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 software memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 oci block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 functional ordered instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 hexadecimal ordered instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 instruction definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 c compiler support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 c header files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 program memory bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 external data memory bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 apb bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7 list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 a product support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 actel customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 actel technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 contacting the customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

revision 2 5 introduction this document describes the archit ecture of a small, general-purpose processor, called the core8051s. this processor is compatible with the instruction se t of the 8051 microcontroller, and preserves the three distinct software memory spaces so that it may be targeted by existing 8051 c compilers. to make it smaller and more flexible than the 8051, the following microcontroller-specific features of the original 8051 are not present: ? sfr-mapped peripherals ? power management circuitry ? serial channel ? i/o ports ?timers the following set of 8051 microcontroller features ar e available in core8051s, but are either optional or reduced in scope: ? multiply and divide instructions (mul, div, and da) ? present by defaul t, but may optionally be implemented as nops ? second data pointer (data pointer 1) ? not enabled by default ? of the 64 kbytes alloca ted to external data memory, 4 kbyt es are allocated to an apb-based peripheral bus and 60 kbytes is allocated to an external data memory interface ? interrupt control logic for 2 interrupts supported actel fpga families for the core8051s are as follows: ? igloo ? /e/plus ? proasic3?/e/l ?fusion ? proasic plus ? ? axcelerator ? ? rtax-s
introduction 6 revision 2 utilization and performance table 1 through table 7 on page 13 give resource usage and performance data for various configurations of core8051s for each type of fpga technology. thes e tables do not cover every possible configuration, but instead list a range of configurations which should give a go od indication of the expected resource usage and performance of the core. abbreviated versio ns of configuration options are used in the tables to aid readability. the meanings of the entries in the debug, program memory access control, data memory access control, and internal ram columns are described in the following paragraphs. debug column ? none: debug logic is not included. ? i/os: debug logic is included and general purpose i/os are used for the debug connection. ? ujtag: debug logic is included and the dedicate d jtag pins of the device and the ujtag macro are used for the debug connection. program memory access control ? ack: acknowledge signal (mem psacki) is used to control access to program memory. ? x: x (where x can range from 0 to 7) wait states are inserted in each access to program memory, instead of using acknowledge control. data memory access control ? ack: acknowledge signal (memacki) is us ed to control accesses to data memory. ? x: x (where x can range from 0 to 7) wait stat es are inserted in each access to data memory, instead of using acknowledge control. internal ram ? instantiated: internal 256x8 ram is implemented using an instantiated ram block. ? inferred: internal 256x8 ram is implemented by inferring ram during synthesis.
core8051s v2.4 handbook revision 2 7 registers registers (fpga tiles) are inferred for the 256x8 ram during synthesis. table 1 ? core8051s utilization and performance for igloo 1.2 v devices (std speed grade) configuration utilization and performance debug include trace ram hardware triggers include second data pointer include mul, div, and da instructions program memory access control data memory access control apb data width internal ram tiles ram blocks mhz none ? ? no yes ack ack 32 instantiated 3,435 1 14.8 i/os no 0 no yes ack ack 32 instantiated 3,833 1 14.9 ujtag no 0 no yes ack ack 32 instantiated 3,792 1 14.4 ujtag no 1 no yes ack ack 32 instantiated 4,080 1 14.7 ujtag no 4 no yes ack ack 32 instantiated 5,029 1 14.4 ujtag yes 0 no yes ack ack 32 instantiated 3,974 3 15.4 ujtag yes 1 no yes ack ack 32 instantiated 4,455 3 14.5 ujtag yes 4 no yes ack ack 32 instantiated 5,538 3 14.6 none ? ? yes yes ack ack 32 instantiated 3,686 1 14.9 none ? ? no yes 2 2 32 instantiated 3,376 1 14.8 none ? ? no yes 5 5 32 instantiated 3,308 1 15.3 none ? ? no yes ack ack 16 instantiated 3,311 1 15.1 none ? ? no yes ack ack 8 instantiated 3,318 1 15.2 none ? ? no yes ack ack 32 inferred 3,457 1 14.7 none ? ? no yes ack ack 32 registers 7,853 0 13.9 ujtag yes 4 yes yes ack ack 32 registers 10,098 2 12.1 none ? ? no no ack ack 8 instantiated 2,849 1 14.7
introduction 8 revision 2 table 2 ? core8051s utilization and performance for igloo 1.5 v devices (std speed grade) configuration utilization and performance debug include trace ram hardware triggers include second data pointer include mul, div, and da instructions program memory access control data memory access control apb data width internal ram tiles ram blocks mhz none ? ? no yes ack ack 32 instantiated 3,110 1 23.9 i/os no 0 no yes ack ack 32 instantiated 3,548 1 22.7 ujtag no 0 no yes ack ack 32 instantiated 3,483 1 24.3 ujtag no 1 no yes ack ack 32 instantiated 3,772 1 23.6 ujtag no 4 no yes ack ack 32 instantiated 4,847 1 23.3 ujtag yes 0 no yes ack ack 32 instantiated 3,742 3 22.9 ujtag yes 1 no yes ack ack 32 instantiated 4,083 3 23.9 ujtag yes 4 no yes ack ack 32 instantiated 5,125 3 23.8 none ? ? yes yes ack ack 32 instantiated 3,318 1 24.2 none ? ? no yes 2 2 32 instantiated 3,386 1 24.2 none ? ? no yes 5 5 32 instantiated 3,357 1 22.9 none ? ? no yes ack ack 16 instantiated 2,995 1 24.5 none ? ? no yes ack ack 8 instantiated 2,915 1 23.9 none ? ? no yes ack ack 32 inferred 3,136 1 24.8 none ? ? no yes ack ack 32 registers 7,633 0 23.3 ujtag yes 4 yes yes ack ack 32 registers 9,917 2 19.9 none ? ? no no ack ack 8 instantiated 2,568 1 23.8
core8051s v2.4 handbook revision 2 9 table 3 ? core8051s utilization and performance for fusion, proasic3, and proasic3e devices (?2 speed grade) configuration utilization and performance debug include trace ram hardware triggers include second data pointer include mul, div, and da instructions program memory access control data memory access control apb data width internal ram tiles ram blocks mhz none ? ? no yes ack ack 32 instantiated 3,324 1 37.1 i/os no 0 no yes ack ack 32 instantiated 3,776 1 36.5 ujtag no 0 no yes ack ack 32 instantiated 3,758 1 35.9 ujtag no 1 no yes ack ack 32 instantiated 4,024 1 37.5 ujtag no 4 no yes ack ack 32 instantiated 4,941 1 35.4 ujtag yes 0 no yes ack ack 32 instantiated 4,053 3 37.1 ujtag yes 1 no yes ack ack 32 instantiated 4,262 3 36.7 ujtag yes 4 no yes ack ack 32 instantiated 5,330 3 36.4 none ? ? yes yes ack ack 32 instantiated 3,546 1 39.9 none ? ? no yes 2 2 32 instantiated 3,356 1 35.9 none ? ? no yes 5 5 32 instantiated 3,335 1 37.9 none ? ? no yes ack ack 16 instantiated 3,190 1 38.7 none ? ? no yes ack ack 8 instantiated 3,081 1 36.9 none ? ? no yes ack ack 32 inferred 3,384 1 37.5 none ? ? no yes ack ack 32 registers 7,739 0 35.9 ujtag yes 4 yes yes ack ack 32 registers 9,937 2 28.9 none ? ? no no ack ack 8 instantiated 2,748 1 37.3
introduction 10 revision 2 table 4 ? core8051s utilization and performance for proasic3l (?1 speed grade) configuration utilization and performance debug include trace ram hardware triggers include second data pointer include mul, div, and da instructions program memory access control data memory access control apb data width internal ram tiles ram blocks mhz none ? ? no yes ack ack 32 instantiated 2,936 1 25.7 i/os no 0 no yes ack ack 32 instantiated 3,360 1 25.4 ujtag no 0 no yes ack ack 32 instantiated 3,261 1 25.1 ujtag no 1 no yes ack ack 32 instantiated 3,624 1 23.9 ujtag no 4 no yes ack ack 32 instantiated 4,637 1 24.5 ujtag yes 0 no yes ack ack 32 instantiated 3,541 3 25.5 ujtag yes 1 no yes ack ack 32 instantiated 3,844 3 24.4 ujtag yes 4 no yes ack ack 32 instantiated 4,926 3 24.7 none ? ? yes yes ack ack 32 instantiated 3,116 1 24.2 none ? ? no yes 2 2 32 instantiated 2,931 1 24.5 none ? ? no yes 5 5 32 instantiated 2,928 1 26.5 none ? ? no yes ack ack 16 instantiated 2,778 1 26.4 none ? ? no yes ack ack 8 instantiated 2,718 1 25.5 none ? ? no yes ack ack 32 instantiated 2,943 1 23.6 none ? ? no yes ack ack 32 instantiated 7,391 0 25.4 ujtag yes 4 yes yes ack ack 32 instantiated 9,755 2 23.1 none ? ? no yes ack ack 8 instantiated 2,444 1 24.9
core8051s v2.4 handbook revision 2 11 table 5 ? core8051s utilization and performance for proasic plus devices (std speed grade) configuration utilization and performance debug include trace ram hardware triggers include second data pointer include mul, div, and da instructions program memory access control data memory access control apb data width internal ram tiles ram blocks mhz none ? ? no yes ack ack 32 instantiated 4,000 1 26.2 i/os no 0 no yes ack ack 32 instantiated 4,318 1 26.4 ujtag no 0 no yes ack ack 32 instantiated 4,271 1 25.8 ujtag no 1 no yes ack ack 32 instantiated 4,709 1 25.7 ujtag no 4 no yes ack ack 32 instantiated 6,004 1 24.4 ujtag yes 0 no yes ack ack 32 instantiated 4,580 4 26.8 ujtag yes 1 no yes ack ack 32 instantiated 5,065 4 23.5 ujtag yes 4 no yes ack ack 32 instantiated 6,368 4 23.5 none - ? yes yes ack ack 32 instantiated 4,344 1 26.8 none - ? no yes 2 2 32 instantiated 4,185 1 27.8 none - ? no yes 5 5 32 instantiated 4,135 1 29.8 none - ? no yes ack ack 16 instantiated 3,821 1 28.1 none - ? no yes ack ack 8 instantiated 3,773 1 28.9 none - ? no yes ack ack 32 inferred 4,056 1 26.2 none - ? no yes ack ack 32 registers 10,888 0 25.2 ujtag yes 4 yes yes ack ack 32 registers 13,652 3 19.9 none ? ? no no ack ack 8 instantiated 3,146 1 28.8
introduction 12 revision 2 table 6 ? core8051s utilization and performance for axcelerator devices (?2 speed grade) configuration utilization and performance debug include trace ram hardware triggers include second data pointer include mul, div, and da instructions program memory access control data memory access control apb data width internal ram tiles ram blocks mhz none ? ? no yes ack ack 32 instantiated 2,111 1 50.9 i/os no 0 no yes ack ack 32 instantiated 2,343 1 44.9 i/os no 1 no yes ack ack 32 instantiated 2,608 1 42.4 i/os no 4 no yes ack ack 32 instantiated 3,197 1 44.1 i/os yes 0 no yes ack ack 32 instantiated 2,554 3 47.4 i/os yes 1 no yes ack ack 32 instantiated 2,797 3 44.1 i/os yes 4 no yes ack ack 32 instantiated 3,413 3 42.5 none ? ? yes yes ack ack 32 instantiated 2,196 1 53.4 none ? ? no yes 2 2 32 instantiated 2,091 1 55.8 none ? ? no yes 5 5 32 instantiated 2,104 1 54.2 none ? ? no yes ack ack 16 instantiated 2,066 1 53.3 none ? ? no yes ack ack 8 instantiated 1,977 1 56.3 none ? ? no yes ack ack 32 inferred 2,104 1 50.1 none ? ? no yes ack ack 32 registers 5,245 0 42.9 i/os yes 4 yes yes ack ack 32 registers 6,714 2 33.1 none ? ? no no ack ack 8 instantiated 1,757 1 53.4
core8051s v2.4 handbook revision 2 13 table 7 ? core8051s utilization and performance for rtax-s devices (?1 speed grade) configuration utilization and performance debug include trace ram hardware triggers include second data pointer include mul, div, and da instructions program memory access control data memory access control apb data width internal ram tiles ram blocks mhz none ? ? no yes ack ack 32 instantiated 2,123 1 39.9 i/os no 0 no yes ack ack 32 instantiated 2,357 1 33.1 i/os no 1 no yes ack ack 32 instantiated 2,607 1 30.1 i/os no 4 no yes ack ack 32 instantiated 3,137 1 28.6 i/os yes 0 no yes ack ack 32 instantiated 2,547 3 29.9 i/os yes 1 no yes ack ack 32 instantiated 2,836 3 33.6 i/os yes 4 no yes ack ack 32 instantiated 3,351 3 26.5 none ? ? yes yes ack ack 32 instantiated 2,192 1 39.7 none ? ? no yes 2 2 32 instantiated 2,057 1 37.8 none ? ? no yes 5 5 32 instantiated 2,118 1 38.4 none ? ? no yes ack ack 16 instantiated 2,042 1 39.6 none ? ? no yes ack ack 8 instantiated 1,987 1 39.4 none ? ? no yes ack ack 32 inferred 2,146 1 38.7 none ? ? no yes ack ack 32 registers 5,224 0 29.2 i/os yes 4 yes yes ack ack 32 registers 6,694 2 22.8 none ? ? no no ack ack 8 instantiated 1,778 1 39.8

revision 2 15 1 ? core8051s overview the core8051s is a high-performance, eight-bit microcontroller ip core. it is a fully functional eight-bit embedded controller that executes all asm51 instru ctions and has the same instruction set as the 80c31. core8051s provides software and hardware interrupts. the core8051s architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. since a cycle is aligned with me mory fetch when possible, most of the one-byte instructions are performed in a single cycle. core 8051s uses one clock per cycle. this leads to an average performance improvement rate of 8.0 (in terms of mips) with respect to the intel device working with the same clock frequency. the original intel 8051 had a 12-clock architecture. a machine cycle needed 12 clocks, and most instructions were either one or tw o machine cycles. therefor e, the 8051 used either 12 or 24 clocks for each instruction, except for the mul and div instru ctions. furthermore, each cycle in the 8051 used two memory fetches. in many cases, the second fetch was a ?dummy? fetch and extra clocks were wasted. table 1-1 shows the speed advantage of core8051s over the standard intel 8051. a speed advantage of 12 in the first column means that core8051s perfor ms the same instruction 12 times faster than the standard intel 8051. the second column in table 1-1 lists the number of types of instructions that have the given speed advantage. the third column lists the total number of instructions that have the given speed advantage. the third column can be thought of as a subcategory of the second column. for example, there are two types of in structions that have a three-ti me speed advantage over the classic 8051, for which there are nine explicit instructions. table 1-1 ? core8051s speed advantage summary speed advantage number of instruction types number of instructions (opcodes) 24 1 1 12 27 83 9.6 2 2 81638 64489 4.8 1 2 41831 329 average: 8.0 sum: 111 sum: 255

revision 2 17 2 ? supported interfaces ports the port signals of core8051s are illustrated in figure 2-1 . figure 2-1 ? core8051s i/o signals clk nsysreset wdogres tck tms tdi trstn membank breakin int0 int1 memdatai mempsacki memacki pready prdata pslverr presetn wdogresn movx tdo breakout trigout auxout dbgmempswr memaddr memdatao mempsrd memwr memrd paddr psel penable pwrite pwdata core8051s
supported interfaces 18 revision 2 the signals listed in table 2-1 are present at the core8051s boundary. table 2-1 ? core8051s ports signal name type polarity/bus size description system signals clk input rise clock input for internal logic. this signal must also be used to clock any apb peripherals, if present. nsysreset input low hardware reset input. a logic zero on this signal for two clock cycles while the oscillator is running resets the device. presetn output low synchronized reset output. this signal should be used to reset any apb peripherals, if present. wdogres input high watchdog timeout indication wdogresn output low reset signal for watchdog movx output high movx instruction executing on-chip debug inte rface (optional) tck input rise jtag test clock. if oci is not used, connect to logic 1. tms input high jtag test mode select. if oci is not used, connect to logic 0. tdi input high jtag test data in. if oci is not used, connect to logic 0. tdo output high jtag test data out trstn input low jtag test reset. if oci is not used, connect to logic 1. membank input 4 optional code memory bank sele ction. if not used, connect to logic 0. breakin input high break bus inpu t. when sampled high, a br eakpoint is generated. if not used, connect to logic 0. breakout output high break bus output. this is driven high when core8051s stops emulation. this can be connected to an open- drain break bus that connects to multiple processors, so that when any cpu stops, all others on the bus are stopped within a few clock cycles. trigout output high trigger output. this signal can be optionally connected to external test equipment to cross-trigger with internal core8051s activity. auxout output high auxiliary output. this signal is an optional genera l purpose output that can be controlled via the oci debugger software. dbgmempswr output high debug program store write. external interrupts int0 input high external interrupt 0 (low priority) int1 input high external interrupt 1 (high priority) external memory bus interface mempsacki input high program memory read acknowledge memacki input high data memory acknowledge memdatai input 8 memory data input memdatao output 8 memory data output memaddr output 16 memory address
core8051s v2.4 handbook revision 2 19 mempsrd output high program store read enable memwr output high data memory write enable memrd output high data memory read enable apb3 interface paddr output 12 this is the apb address bus. psel output 1 this signal indi cates that the slave device is selected and a data transfer is required. penable output high this strobe signal is used to time all accesses on the peripheral bus. the enable signal is used to indicate the second cycle of an apb transfer. the rising edge of penable occurs in the middle of the apb transfer. pwrite output high when high, this signal i ndicates an apb write access. when low, it indicates an apb read access. prdata input 8, 16, or 32 the read data bus is driven by the selected slave during read cycles (when pwrite is low). the width of this bus matches the width of the widest peripheral in the system. pwdata output 8, 16, or 32 the write data bus is driven by the core8051s during write cycles (when pwrite is high). the width of this bus matches the width of the widest peripheral in the system. pready input 1 this signal is the ready si gnal for the apb inte rface. this signal conforms to apb version 3.0. using this signal, apb slave peripherals can stall reads or writes, if not ready to complete the transaction. pslverr input 1 this signal is specified in v3.0 of the apb specificati on. it is currently unused in core8051s. table 2-1 ? core8051s ports (continued) signal name type polarity/bus size description
supported interfaces 20 revision 2 interface descriptions parameters/generics the verilog parameters or vhdl generics shown in ta b l e 2 - 2 are present in the core8051s rtl code. these may be modified by the user to confi gure core8051s as required. when working with smartdesign, these parameters/generics are set to appropriate values using the core8051s configuration window. table 2-2 ? table x. core8051s parameters/generics parameter/generic default value description debug 0 0 = on-chip instrumentation (oci) debug logic not included. 1 = oci debug logic included; general purpose fpga i/os used for debug connection 2 = oci debug logic included, dedicated jtag pins of device (along with ujtag macro) used for debug connection incl_trace 0 0 = trace ram not included 1 = trace ram included trig_num 0 number of hardware triggers. possible settings are 0, 1, 2, or 4. incl_dptr1 0 0 = second data pointer not included. 1 = second data pointer included. incl_mul_div 1 0 = mul, div, and da instructions not included. 1 = mul, div, and da instructions included. variable_wait 1 0 = program store memory related acknowledge input (mempsacki) not used for cont rolling accesse s to program memory. a fixed number of wait states (defined by wait_val parameter) is used for each access to program memory. wait_val 0 this setting is only used when variable_wait = 0 and defines the (fixed) number of wait states inserted in each access to program memory. possible values are 0 to 7. variable_stretch 1 0 = data memory related acknowledge input (memacki) not used for controlling accesses to program memory. a fixed number of wait states (defined by wait_val parameter) is used for each access to program memory. 1 = data memory related acknowledge input (memacki) is used for controlling accesses to program memory. stretch_val 1 this setting is only used when variable_stretch = 0 and defines the (fixed) number of wait states inserted in each access to data memory. possible values are 0 to 7. apb_dwidth 32 data width in number of bits for apb bus. possible settings are 8, 16, or 32. intram_implementation 0 this parameter is us ed to control how the internal (256x8) ram is implemented. possible settings are: 0 = instantiate ram block 1 = infer ram block during synthesis 2 = infer registers for ram during synthesis
revision 2 21 3 ? tool flows smartdesign core8051s is available for download to the smartd esign ip catalog via the libero? integrated design environment (ide) web repository. for information on using smartdesign to instantiate, configure, connect, and generate cores, refer to the libero ide online help. the advanced peripheral bus (apb) version 3 interfac e of core8051s will typically be connected to the mirrored master interface of co reapb3, with various apb or apb3 slaves connected to the slave interfaces of coreapb3. the external memory in terface (externalmemif) of core8051s must be connected to program and data memories, which can be implemented either on-c hip or off-chip. if debug functionality is enabled, the jtag signals (tck, tms, tdi, tdo, and trstn) of the debug interface (debugif) must be routed to the top level of your des ign. either the dedicated jtag pins of the device or general purpose i/o pins can be used for the jtag debug connection. the ujtag macro is employed when the dedicated jtag pins are used for the debug connection. figure 3-1 shows the core8051s configuration window, alon g with cross-references to the corresponding top-level parameters. the parameters/generics of the core are fully described in the "parameters/generics" section on page 20 . figure 3-1 ? core8051s configuration window debug intram_implementation incl_trace trig_num incl_dptr1 incl_mul_div_da variable_wait wait_val variable_stretch stretch_val apb_dwidth
tool flows 22 revision 2 the configuration options for core8051s are descr ibed in the following paragraphs. the core8051s configuration window is used to adjust the values of the underlying parameters/generics in the rtl code for the core. each configuration option presented in the configuration window corresponds directly to an actual parameter/generic in the rtl code for core8051s. debug configuration ? there are three debug-related configuration options. set the debug option to choose to enable or disable on-chip instrumentation (oci) debug functionality and to control how any debug connection is implemented. when this functionalit y is enabled, you can connect a debugger to the processor via a jtag connection. you can disable th e debug functionality if you do not intend to use a debugger and want to minimize the number of tiles consumed by the processor. there are two possibilities for implementing the jtag connection. from the debug drop-down menu, choose one of these options: ? disabled to exclude debug functionality ? enabled using ujtag to include debug functionality and to use the dedicated jtag pins of the device (via the ujtag macro) for the debug connec tion. this setting is mostly used when only one debug connection is required. with this sett ing you can make use of the flashpro3 or low- cost programming stick (lcps) connection for the debug connection. ? enabled using i/os to include debug functionality and to use general purpose i/o pins for the debug connection. select this option if the ujtag ma cro is either not presen t on your device or is already in use and not available for the core8051s debug connection. ? when debug is set to enabled using ujtag or enabled using i/os , two additional debug options are available for added control over the debug functionality to be included: ?select include trace ram to include a 256-byte deep trace ram within core8051s. no trace ram is present if this option is not selected. including the trace ram increases the tile count for the processor and consumes ram blocks on the device. ?set number of hardware triggers/breakpoints to 0, 1, 2, or 4 to set the maximum number of hardware triggers/breakpoints available when debugging a core8051s system. increasing the number of hardware triggers/breakpoints incr eases the tile count of the processor. optional registers and instructions select include second data pointer to include a second data pointer. when this option is selected, two additional special function registers (sfrs) are incl uded to implement the second (16-bit) data pointer. select include mul, div, and da instructions to include the multiply, divide, and decimal adjust instructions. if the software to be run on the proc essor does not make use of the mul, div, and da instructions, this option check box can be cleared to r educe the tile count of the core. the behavior of the processor is undefined when attempting to execute a mul, div or da instruction while the processor is not configured to include suppo rt for these instructions. program memory access there are two possible methods for controlling accesses by the processor to program memory: ?select mempsacki-controlled program memory when the mempsacki (program store memory acknowledge input) signal is used to control accesses to progr am memory. when this option is select ed, the program memory or memory sub system must assert mempsacki when a write to program memory has completed and when valid read data is available. ? clear the check box for mempsacki-controlled program memory and set a fixed number of wait cycles for each access to program memory by adjusting th e program memory wait cycles option. note: program memory wait cycles is only enabled when mempsacki-controlled program memory is not selected.
core8051s v2.4 handbook revision 2 23 external data memory access there are two possible methods for controlling accesses by the processor to external data memory. ?select memacki-controlled external data memory when the memacki (data memory acknowledge input) signal is used to control accesses to data memory. when this option is selected, the data memory or memory subsystem must assert memacki when a write to data memory has completed and when valid read data is available. ? clear the check box for memacki-controlled external data memory and set a fixed number of wait cycles for each access to data memory by adjusting the external data memory stretch cycles option. note: note that the external data memory stretch cycles is only enabled wh en memacki-controlled external data memory is not selected. the external data memory is external to the proc essor but can be implemented using either on-chip or off-chip memory resources. other options set apb data width to 8 bit , 16 bit , or 32 bit to select the appropriate da ta width for the apb interface of the processor. when the apb data widt h is 16 bits or 32 bits, extr a sfrs are used to store the upper bytes of apb data when the (8-bit ) processor core carries out an access to apb space. see the "external data memory space" section on page 30 for more informati on on the apb interface. the internal ram (256x8) implementation option is used to control how the internal 256x8 ram is implemented. three choices are available: ? instantiate ram block : a ram macro block is directly instantiated in the rtl code. ? infer ram block during synthesis : a synthesis directive (in the form of a structured comment) is used in the rtl code to cause the synthesi s tool to infer ram during synthesis. a ram macro block will be used in this case, which means that this choice gives a very similar outcome to instantiate ram block. ? infer registers for ram during synthesis : a synthesis directive (in the form of a structured comment) is used in the rtl code to cause the synthesis tool to use registers (fpga tiles) to implement the 256x8 internal ram. this consider ably increases the tile co unt for the core but has the benefit of enhancing the fault-to lerant capabilities of core8051s.
tool flows 24 revision 2 example system a typical system that inclu des core8051s is shown in figure 3-2 . connections can be made automatically in smartdesign us ing the auto connect menu option. simulation core8051s comes with a verification testbench and also supports bus functional model (bfm)-based simulation of a system in which it is instantiated. the bfm only simulates transactions on the apb interface of core8051s and does implement a complete model of the processor. it is not possible to simulate code running on the processor with a bfm-based simulation. core8051s simulation can be invoked from the li bero ide project manager. after the design has been generated, click the simulation button in the libero ide to run a simulation. the core8051s component must be set as the des ign root (right-click core8051s and select set as root ), before running a core8051s simulation. however, if intending to run a bfm-based simulation, you must first compile the component which instantiates co re8051s. to do this, set the design root one level of hierarchy above the core8051s component and click the simulation button to invoke modelsim? and compilation of the relevant components. when the (automatically generated) modelsim script finishes, exit modelsim. now set the design root to the core8051s component and click the simulation button again. this enables you to run a bfm-based simulation of your core8051s system. the core8051s verification testbench can be run directly, with out the need to first compile the component that instantiates core8051s. the following message will appear in the modelsim transcript window when running (pre-synthesis) core8051s simulation: the following (pre-synthesis) simulation options are available for your core8051s-based system: bfm - apb bus functional model (bfm-driven) simulation of your system oci - run core8051s on chip instrumentation (oci) tests opcode - run core8051s opcode test suite, consisting of 256 opcode tests - enter a number in the range 1 to 256 to run a specific opcode test enter "bfm", "oci", "opcode" or a number between 1 and 256 and hit return key to select simulation type figure 3-2 ? example system including core8051s
core8051s v2.4 handbook revision 2 25 follow the instructions in the modelsim transcript wi ndow to choose the type of simulation to run. bfm- based simulation is not support ed after synthesis has been run and bfm does not appear as a simulation option in the post-synthesis modelsim message, which is shown below: the following (post-synthesis) simulation options are available for your core8051s-based system: oci - run core8051s on chip instrumentation (oci) tests opcode - run core8051s opcode test suite, consisting of 256 opcode tests - enter a number in the range 1 to 256 to run a specific opcode test (note: bfm-driven simulation not available post-synthesis) enter "oci", "opcode" or a number between 1 and 256 and hit return key to select simulation type bfm-based simulation when running a bfm-based simulation of a co re8051s system, a bfm command script is used to control the simulation. this command script is dy namically generated by sm artdesign, based on the components connected to the apb interface of co re8051s. the command script file is named subsystem.bfm and is located in the simulation folder. you can modify the command script, refer to "bfm-script language" for details on the syntax used in the file. during simulation, the bfm generate s a series of transfers on the apb bus. these write to and read from registers within peripherals attached to the apb bus, of which core8051s is master . this verifies that the apb interface is fully operational. the bfm tests do no t perform any verification on the core8051s itself. the advantage of bf m-driven simulation is that you can exer cise the system using a simple scripting language, before writing any c code or 8051 assembler code. bfm-script language the following script commands are defined for use by the bfm: memmap this command is used to asso ciate a label, r epresenting a system resource, with a memory map location. the other bfm script co mmands may perform accesses to loca tions within this resource by referencing this label and a register offset relative to this base address. syntax memmap resource_name base_address; ? resource_name: this is a string containing the user-friendly instance name of the resource being accessed. for bfm scripts generated automatical ly by smartdesign, this name corresponds to the instance name of the associated core in the generated subsystem verilog or vhdl. ? base_address: this is the base address of the resource, in hexadecimal format. write this command causes the bfm to perform a write to a specified offset, within the memory map range of a specified system resource. syntax write width resource_name byte_offset data; ? width: this takes on the enumerated values of w, h, or b, for word, halfword, or byte. ? resource_name: this is a string containing the user-friendly instance name of the resource being accessed. ? byte_offset: this is the offset from the base of the resource, in bytes. it is specified as a hexadecimal value. ? data: this is the data to be written. it is specified as a hexadecimal value. example write w videocodec 20 11223344;
tool flows 26 revision 2 read this command causes the bfm to perform a read of a specified offset, within the memory map range of a specified system resource. syntax read width resource_name byte_offset; ? width: this takes on the enumerated values of w, h, or b, for word, halfword, or byte. ? resource_name: this is a string containing the user-friendly instance name of the resource being accessed. ? byte_offset: this is the offset from the base of the resource, in bytes. it is specified as a hexadecimal value. example read w videocodec 20; readcheck this command causes the bfm to perform a read of a specified offset, within the memory map range of a specified system resource, and to compare the read value with the expected value provided. syntax readcheck width resource_name byte_offset data; ? width: this takes on the enumerated values of w, h, or b, for word, halfword, or byte. ? resource_name: this is a string containing the user-friendly instance name of the resource being accessed. ? byte_offset: this is the offset from the base of the resource, in bytes. it is specified as a hexadecimal value. ? data: this is the expect ed read data. it is specified as a hexadecimal value. example readcheck w videocodec 20 11223344; poll this command continuously reads a specified lo cation until a requested value is obtained. this command allows one or more bits of the read data to be masked out. this allows, for example, poll waiting for a ready bit to be set, while ignoring the values of the other bits in the location being read. syntax poll width resource_name byte_offset data bitmask; ? width: this takes on the enumerated values of w, h, or b, for word, halfword, or byte. ? resource_name: this is a string containing the user-friendly instance name of the resource being accessed. ? byte_offset: this is the offset from the base of the resource, in bytes. it is specified as a hexadecimal value. ? bitmask: the bitmask is anded with the read data and the result is then compared to the bitmask itself. if equal, then all the bits of interest are at their required value and the poll command is complete. if not equal, then the polling continues. wait this command causes the bfm script to st all for a specified number of clock periods. syntax wait num_clock_ticks; ? num_clock_ticks: this is the number of clock periods during which th e bfm stalls (does not initiate any bus transactions). waitint0 this command causes the bfm to wait until an interru pt event (low to high transition) is seen on the int0 pin before proceeding with the exec ution of the remainder of the script.
core8051s v2.4 handbook revision 2 27 syntax waitint0; waitint1 this command causes the bfm to wait until an interru pt event (low to high transition) is seen on the int1 pin before proceeding with the exec ution of the remainder of the script. syntax waitint1; synthesis in libero ide to run synthesis on the core with the parameter settings selected in smartdesign, set the design root appropriately, and click the synthesis button in the project manager . the synthesis window appears, displaying the synplicity ? project. to perform synthesis, click the run button. place-and-route in libero ide after setting the design root appropriately and running synthesis, click the layout button in the project manager to invoke designer. core8051s requi res no special place-and-route settings.

revision 2 29 4 ? core8051s features software memory map the core8051s microcontroller uti lizes the harvard architecture, with separate code and data spaces. memory organization in core8051s is similar to t hat of the industry standard 8051. there are three memory areas, as shown in figure 4-1 : ? program memory (internal ram, external ram, or external rom) ? external data memory (external ram) ? internal data memory (internal ram) the software memory map for the core8051s is shown in figure 4-1 . as far as the software programmer is concerned, ther e are three distinct memory spaces available, as shown in figure 4-1 . program memory core8051s can address up to 64 kbytes of program memory space, from 0000h to ffffh. the external memory bus interface ( table 4-1 on page 31 ) services program memory when the mempsrd signal is active. program memory is read when the cpu performs fetching instructions or movc. after reset, the cpu starts program execution from location 0000h . the lower part of the program memory includes interrupt and reset vectors. the inte rrupt vectors are spaced at eight-byt e intervals, starting from 0003h. program memory can be implemented as internal ram, external ram, external rom, or a combination of all three. writing to external program memory is only supported in debug mode, using the oci logic block and external debugger hardware and software. the program memory can use variab le length accesses (mempsacki-con trolled), or a fixed number of wait cycles may be inserted on each read. refer to "program memory access" on page 22 for more information about configuring access to program memory. figure 4-1 ? core8051s software memory map 256 locations 256 locations 256 locations peripheral 1 peripheral 15 peripheral 0 word-addressable only nvm external data ram 64 kbytes external data memory 60 kbytes external program memory internal data memory internal ram sfr subset 128 bytes 128 bytes
core8051s features 30 revision 2 external data memory space core8051s can address up to 64 kbytes of external data memory space, from 0000h to ffffh. this memory is external to the core, not necessarily to the fpga. in the core 8051s, the upper 4 kbytes (f000h to ffffh) of external data memory spac e is mapped to an apb bus. the lower 60 kbytes is mapped to the external memory bus interface. external data interface the external memory bus interface ( table 2-1 on page 18 ) services data memory when the memrd signal is active. core8051s writes into external data memory when the cpu executes movx @ri,a or movx @dptr,a instructions. the external data memo ry is read when the cpu executes movx a,@ri or movx a,@dptr instructions. there is improved vari able length of the movx instructions to access fast or slow external ram and external peripherals. the external data memory can use variable length accesses (memacki-controlled), or a fixed number of stretch cycles may be inserted on each read or write. refer to "external data memory access" on page 23 for more information about configuring access to external data memory. apb interface core8051s based systems use an apb bus for connecting peripherals, where the core8051s acts as the bus master. the width of the apb bus on core8051s can be selected to match the width of the widest apb peripheral in the system (8, 16, or 32 bits). as the core8051s is an 8-bit processor and it is not possible to indicate transaction size on the apb, reads and writes from or to the apb bus in 16-bit or 32- bit mode are accomplished by means of newly defined sfrs, hereafter referred to as x registers. for example, to perform a write to a 32-bit apb peripheral, the program running on the core80 51s must first perform three individual 8-bit writes to x registers (xwb1, xwb2, and xwb3). these registers hold the value to be written out on pwdata [31:8]. when the program subsequently does a write to the apb address in question, the 8 bits of the write data associated with t hat write cycle are put out on the pwdata [7:0] and the three writ e ?x registers? are put onto the apb bus as pwdata [31:8]. 16-bit and 32-bit reads from the apb are handled in a similar manner. to perform a 32-bit read from an apb location, the program must perform a read of t he apb location, from which it immediately obtains bits [7:0] of the 16 or 32 bits on prdata[7:0]. subsequently, the program must read the three read x registers (xrb1, xrb2, and xrb3) to get bits [31: 8], which were read from the apb peripheral and latched in these sfrs at th e time of the apb transaction. for the 4 kbytes of memory space allocated to the apb interface, onl y word access is possible, where word refers to an 8-bit, 16-b it, or 32-bit entity, for their respective apb bus implementations. the apb interface of core8051s will typically be connected to coreapb3, which can in turn connect to up to 16 peripherals such as coretimer and core gpio. often the programmer accessible registers in these peripherals will be located at 32-bit word boundaries in the address map. this means that consecutive registers are located at address offset s 0x00, 0x04, 0x08, 0x0c, and so on. core8051s must take account of this when accessing such peripher als. for example, to access successive register locations in a peripheral attach ed to slave slot 0 on coreapb3, core8051s would issue addresses 0xf000, 0xf004, 0xf008, 0xf00c, and so on. the net effect is that only every f ourth location in the apb space is usable if the perip herals are designed such that their registers are located at 32-bit word boundaries in the memory map. if all of the 4 kbytes of apb space connects to peripherals of this type, t hen there are only 1,024 separately addressable locations, which equates to 64 locations per peripheral, assuming coreapb3 is used. note that the apb data width is independent of the addressing scheme. each location can hold a value which is 8, 16, or 32 bits wide. the apb data width configurable option of core8051s should be set to match the largest data width to be accessed on the apb interface.
core8051s v2.4 handbook revision 2 31 internal data memory space internal ram the internal data memory space services 256 bytes of data ram and 128 bytes of sfrs. the internal data memory address is always one byte wide. the memory space is 256 bytes large (00h to ffh). direct or indirect addressing acce sses the lower 128 bytes of inte rnal ram. indirect addressing accesses the upper 128 bytes of internal ram. the lower 128 bytes contain work registers and bi t-addressable memory. the lower 32 bytes form four banks of eight registers (r0?r7). two bits on the program memory status word (psw) select which bank is in use. the next 16 bytes form a block of bit-addressable memory space at bit addressees 00h?7fh. sfr registers the sfrs occupy the upper 128 bytes of internal data memory space. this sfr area is available only by direct addressing. table 4-1 lists the sfr registers present in core8051s. the above table contains the minimal subset of sf r registers (sp, dpl, dph, psw, acc, and b) that are required to support existing c compilers. ther e is an optional second data pointer (not available by default). there are also six non-st andard sfr registers shown, referred to hereafter as x registers. the xwb1 and xrb1 registers are present only if apb_ dwidth is 16 or greater. xwb2, xwb3, xrb2, and xrb3 are present only if apb_dwidth is 32. they are used to provide write data and latch read data for the upper 3 bytes of th e apb bus, if present, during a movx inst ruction to apb memory space (within external data memory space). the six x registers are not bit-addressable. note also that the x registers are read/write. this is necessary to handle the situati on where an isr needs to access the apb bus, but has interrupted between the user setting up the x regi sters and performing the movx (on an apb write), or between the movx and r eading of the x registers (on an apb re ad). the recomme nded behavior for an isr is to read the x registers on entry into the isr and to restore them to their original values on exiting the isr. table 4-1 ? core8051s sfr registers register location description sp 0x81 stack pointer dpl 0x82 data pointer 0 low dph 0x83 data pointer 0 high dpl1 0x84 data pointer 1 low (optional) dph1 0x85 data pointer 1 high (optional) icon 0x88 interrupt control register dps 0x92 data pointer select (optional) xwb1 0x9a external write buffer 1 (optional) xwb2 0x9b external write buffer 2 (optional) xwb3 0x9c external write buffer 3 (optional) xrb1 0x9d external read buffer 1 (optional) xrb2 0x9e external read buffer 2 (optional) xrb3 0x9f external read buffer 3 (optional) ie 0xa8 interrupt enable register psw 0xd0 program status word (bit-addressable) acc 0xe0 accumulator (bit-addressable) b 0xf0 b register (bit-addressable)
core8051s features 32 revision 2 accumulator (acc) the acc register is the accumulato r. most instructions use the accu mulator to hold the operand. the mnemonics for accumulator-specif ic instructions refer to the accumulator as a, not acc. b register (b) the b register is used during multiply and divide instructions. it can also be used as a scratch-pad register to hold temporary data. program status word (psw) the psw register flags and bit functions are listed in ta b l e 4 - 2 and table 4-3 . the state of bits rs1 and rs0 from the psw register select the working registers bank as listed in ta b l e 4 - 4 . stack pointer (sp) the stack pointer is a one-byte register initialized to 07h after reset. this register is incremented before push and call instructions, causing the stack to begin at location 08h. data pointer (dptr) the data pointer (dptr) is two bytes wide. the lower pa rt is dpl, and the highest is dph. it can be loaded as a two- byte register (mov dptr,#data16) or as two registers (e.g. mov dpl,#data8). it is generally used to access external code or data space (e .g. movc a,@a+dptr or mov a,@dptr respectively). program counter (pc) the program counter is two bytes wide, and is init ialized to 0000h after reset. this register is incremented during fetching operation code or operation data from program memory. table 4-2 ? psw register flags cy ac f0 rs1 rs ov ? p table 4-3 ? psw bit functions bit symbol function 7 cy carry flag 6 ac auxiliary carry flag for bcd operations 5 f0 general purpose flag 0 available for user 4 rs1 register bank select control bit 1, used to select working register bank 3 rs0 register bank select control bit 0, used to select working register bank 2 ov overflow flag 1 ? user defined flag 0 p parity flag, affected by hardware to indicate odd / even number of "one" bits in the accumulator, i.e. even parity table 4-4 ? rs1/rs0 bit selections rs1/rs0 bank selected location 00 bank 0 (00h ? 07h) 01 bank 1 (08h ? 0fh) 10 bank 2 (10h ? 17h) 11 bank 3 (18h ? 1fh)
core8051s v2.4 handbook revision 2 33 interrupt enable register (ie) the interrupt enable register is a on e-byte register initialized to 00h after reset. the ie bit functions are listed in ta b l e 4 - 5 . note that the eal and ex0 bits must both be set to 1 to enable the int0 interrupt. similarly, eal and ex1 must both be set to 1 to enable the int1 interrupt. interrupt control register (icon) the interrupt control register is a one-byte register initialized to 00h after reset. the icon bit functions are listed in ta b l e 4 - 6 . the icon register implements a subset of the timer control (tcon) register, which is commonly present in implementations of the 8051 processor. table 4-5 ? bit functions bit symbol default value function 7 eal 0 0 = disable all interrupts 6 ? 0 unused 5 ? 0 unused 4 ? 0 unused 3 ? 0 unused 2 ex1 0 0 = disable external interrupt 1 (int1) 1 ? 0 unused 0 ex0 0 0 = disable external interrupt 0 (int0) table 4-6 ? bit functions bit symbol default value function 7 ? 0 unused 6 ? 0 unused 5 ? 0 unused 4 ? 0 unused 3 ie1 0 interrupt 1 event flag. when it1 = 0, this flag follows the level on the int1 input. when it1 = 1, this flag is set when a rising edge is observed on interrupt input int1, and is cleared when the interrupt is processed. 2 it1 0 interrupt 1 type control bit. this bit selects whether a rising edge or a high level on input pin int1 causes an interrupt. 0 = high level causes interrupt. 1 = rising edge causes interrupt. 1 ie0 0 interrupt 0 event flag. when it0 = 0, this flag follows the level on the int0 input. when it0 = 1, this flag is set when a rising edge is observed on interrupt input int0, and is cleared when the interrupt is processed. 0 it0 0 interrupt 0 type control bit. this bit selects whether a rising edge or a high level on input pin int0 causes an interrupt. 0 = high level causes interrupt. 1 = rising edge causes interrupt
core8051s features 34 revision 2 interrupts core8051s has two interrupt inputs, int0 and int1. in t0 is low priority (priority level 0), with a vector address of 03h. int1 is high priority (prior ity level 1), with a vector address of 13h. note: if using the keil c51 c compiler, an interrupt func tion attribute of 0 must be used for int0 and an attribute of 2 for int1. the interrupt enable (ie) and interrupt control (icon) special function registers are used to determine interrupt behavior. interrupts can be individually or collectively enabl ed or disabled using the interrupt enable register. the interrupt control register contains an event fl ag and a type control bit for the int0 and int1 interrupts. each type control bit is used to control whether the corresponding interrupt is rising edge or level high sensitive, with the default being level high se nsitive. each event flag is set to 1 when a rising edge or high level is detected on the corresponding interrupt input. when rising edge sensitive operation is selected (by se tting the type control bit to 1), the relevant event flag will be automatically cleared when the interrupt is serviced. this automatic clearing of the event flags is made possible by logic in the processor that dete cts vectoring to address 03h (in the case of an int0 interrupt) or 13h (in the case of an int1 interrupt). when level sensitive interrupt opera tion is selected, the relevant ev ent flag is not cleared when the interrupt is serviced and remains asserted until the source of the interrupt is cleared. the event flag effectively follows the (int0 or int1) interrupt i nput when level sensitive operation is selected. the interrupt service routine must clear the source of th e interrupt when level sensitive interrupts are used. oci block the on-chip instrumentation (oci) block communicates with external debugger hardware and software as a debugging aid to the user. the oci debug block can be optionally included, refer to "debug configuration" on page 22 for more information on debug related configuration options. the following debug features are pr esent in core8051s: ? run/stop control ? single-step mode ? software breakpoint ? execution of a debugger program ? hardware breakpoint ? program trace ? access to acc (accumulator) register
revision 2 35 5 ? instruction set the core8051s instructions are binary code compatible and perform the same functions as the industry- standard 8051. this is the asm51 instruction set. so me of these instructions , however, are not enabled by default and so must be expl icitly enabled if required. table 5-1 and table 5-2 contain notes for mnemonics used in the various instruction set tables. in table 5-3 on page 36 through table 5-7 on page 40 , the instructions are ordered in functional groups. in table 5-8 on page 41 , the instructions are ordered in the hex adecimal order of the operation code. for more detailed information about the core8051s instruction set, refer to the core8051 instruction set details user?s guide . table 5-1 ? notes on data addressing modes rn working register, r0?r7 direct 128 internal ram locations, any i/o port, control or status register @ri indirect internal or external ram location addressed by register, r0 or r1 #data 8-bit constant included in instruction #data 16 16-bit constant included as bytes 2 and 3 of instruction bit 128 software flags, any bit-addre ssable i/o pin, control or status bit a accumulator table 5-2 ? notes on programming addressing modes addr16 destination address for lcall and ljmp may be anywhere within the 64 kbytes program memory address space. addr11 destination address for acall and ajmp will be within the same 2 kbytes page of program memory as the first byte of the following instruction. rel sjmp and all conditional jumps include an 8-bit offset byte. range is from plus 127 to minus 128 bytes, relative to the firs t byte of the following instruction.
instruction set 36 revision 2 functional ordered instructions table 5-3 through table 5-7 on page 40 list the functional ordered instructions. table 5-3 ? arithmetic instructions mnemonic description byte cycle add a,rn adds the register to the accumulator. 1 1 add a,direct adds the direct byte to the accumulator. 2 2 add a,@ri adds the indirect ram to the accumulator. 1 2 add a,#data adds the immediate data to the accumulator. 2 2 addc a,rn adds the register to the accumulator with a carry flag. 1 1 addc a,direct adds the direct byte to a with a carry flag. 2 2 addc a,@ri adds the indirect ram to a with a carry flag. 1 2 addc a,#data adds the immediate data to a with carry a flag. 2 2 subb a,rn subtracts the register from a with a borrow. 1 1 subb a,direct subtracts the direct byte from a with a borrow. 2 2 subb a,@ri subtracts the indirect ram from a with a borrow. 1 2 subb a,#data subtracts the immediate data from a with a borrow. 2 2 inc a increments the accumulator. 1 1 inc rn increments the register. 1 2 inc direct increments the direct byte. 2 3 inc @ri increments t he indirect ram. 1 3 dec a decrements the accumulator. 1 1 dec rn decrements the register. 1 1 dec direct decrements the direct byte. 1 2 dec @ri decrements the indirect ram. 2 3 inc dptr increments the data pointer. 1 3 mul a,b multiplies a and b. 1 5 div a,b divides a by b. 1 5 da a decimal adjust accumulator 1 1
core8051s v2.4 handbook revision 2 37 table 5-4 ? logic operations mnemonic description byte cycle anl a,rn and register to accumulator 1 1 anl a,direct and direct byte to accumulator 2 2 anl a,@ri and indirect ram to accumulator 1 2 anl a,#data and immediate data to accumulator 2 2 anl direct,a and accumulator to direct byte 2 3 anl direct,#data and immediate data to direct byte 3 4 orl a,rn or register to accumulator 1 1 orl a,direct or direct byte to accumulator 2 2 orl a,@ri or indirect ram to accumulator 1 2 orl a,#data or immediate data to accumulator 2 2 orl direct,a or accumulator to direct byte 2 3 orl direct,#data or immediate data to direct byte 3 4 xrl a,rn exclusive or register to accumulator 1 1 xrl a,direct exclusive or direct byte to accumulator 2 2 xrl a,@ri exclusive or indi rect ram to accumulator 1 2 xrl a,#data exclusive or immediate data to accumulator 2 2 xrl direct,a exclusive or accumulator to direct byte 2 3 xrl direct,#data exclusive or im mediate data to direct bytre 3 4 clr a clears the accumulator. 1 1 cpl a complements the accumulator. 1 1 rl a rotates the accumulator left. 1 1 rlc a rotates the accumulator left through carry. 1 1 rr a rotates the accumulator right. 1 1 rrc a rotates the accumulator right through carry. 1 1 swap a swaps nibbles within the accumulator. 1 1
instruction set 38 revision 2 table 5-5 ? data transfer operations mnemonic description byte cycle mov a,rn moves the register to the accumulator. 1 1 mov a,direct moves the direct byte to the accumulator. 2 2 mov a,@ri moves the indirect ram to the accumulator. 1 2 mov a,#data moves the immediate data to the accumulator. 2 2 mov rn,a moves the accumula tor to the register. 1 2 mov rn,direct moves the direct byte to the register. 2 4 mov rn,#data moves the immediate data to the register. 2 2 mov direct,a moves the accumula tor to the direct byte. 2 3 mov direct,rn moves the register to the direct byte. 2 3 mov direct,direct moves the direct byte to the direct byte. 3 4 mov direct,@ri moves the indirect ram to the direct byte. 2 4 mov direct,#data moves the immediate data to the direct byte 3 3 mov @ri,a moves the accumulator to the indirect ram. 1 3 mov @ri,direct moves the direct byte to the indirect ram. 2 5 mov @ri,#data moves the immediate data to the indirect ram. 2 3 mov dptr,#data16 loads the data pointer with a 16-bit constant. 3 3 movc a,@a + dptr moves the code byte relative to the dptr to the accumulator. 1 3 movc a,@a + pc moves the code byte relative to the pc to the accumulator. 1 3 movx a,@ri moves the external ram (8-bit address) to a. 1 3?10 movx a,@dptr moves the external ram (16-bit address) to a. 1 3?10 movx @ri,a moves a to the external ram (8-bit address). 1 4?11 movx @dptr,a moves a to the external ram (16-bit address). 1 4?11 push direct pushes the direct byte onto the stack. 2 4 pop direct pops the direct byte from the stack. 2 3 xch a,rn exchanges the register with the accumulator. 1 2 xch a,direct exchanges the direct byte with the accumulator. 2 3 xch a,@ri exchanges the indirect ram with the accumulator. 1 3 xchd a,@ri exchanges the low-order nibble indirect ram with a. 1 3
core8051s v2.4 handbook revision 2 39 table 5-6 ? boolean manipulation operations mnemonic description byte cycle clr c clears the carry flag. 1 1 clr bit clears the direct bit. 2 3 setb c sets the carry flag. 1 1 setb bit sets the direct bit. 2 3 cpl c complements the carry flag. 1 1 cpl bit complements the direct bit. 2 3 anl c,bit and direct bit to the carry flag. 2 2 anl c,bit and complements of direct bit to the carry. 2 2 orl c,bit or direct bit to the carry flag. 2 2 orl c,bit or complements of direct bit to the carry. 2 2 mov c,bit moves the direct bit to the carry flag. 2 2 mov bit, c moves the carry flag to the direct bit. 2 3
instruction set 40 revision 2 table 5-7 ? program branch operations mnemonic description byte cycle acall addr11 absolute subroutine call 2 6 lcall addr16 long subroutine call 3 6 ret return return from subroutine 1 4 reti return return from interrupt 1 4 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a + dptr jump indirect relative to the dptr 1 2 jz rel jump if accu mulator is zero 2 3 jnz rel jump if accumu lator is not zero 2 3 jc rel jump if carry flag is set 2 3 jnc rel jump if carry flag is not set 2 3 jb bit,rel jump if direct bit is set 3 4 jnb bit,rel jump if direct bit is not set 3 4 jbc bit,rel jump if direct bit is set and clears bit 3 4 cjne a,direct,rel compares direct byte to a and jumps if not equal. 3 4 cjne a,#data,rel compares immediate to a and jumps if not equal. 3 4 cjne rn,#data rel compares immediate to the register and jumps if not equal. 3 4 cjne @ri,#data,rel compares immediate to indirect and jumps if not equal. 3 4 djnz rn,rel decrements register and jumps if not zero. 2 3 djnz direct,rel decrements direct byte and jumps if not zero. 3 4 nop no operation 1 1
core8051s v2.4 handbook revision 2 41 hexadecimal ordered instructions the core8051s instructions are listed in ta b l e 5 - 8 in order of hexadecima l opcode (operation code). table 5-8 ? core8051s instruction set in hexadecimal order opcode mnemonic opcode mnemonic 00h nop 10h jbc bit,rel 01h ajmp addr11 11h acall addr11 02h ljmp addr16 12h lcall addr16 03h rr a 13h rrc a 04h inc a 14h dec a 05h inc direct 15h dec direct 06h inc @r0 16h dec @r0 07h inc @r1 17h dec @r1 08h inc r0 18h dec r0 09h inc r1 19h dec r1 0ah inc r2 1ah dec r2 0bh inc r3 1bh dec r3 0ch inc r4 1ch dec r4 0dh inc r5 1dh dec r5 0eh inc r6 1eh dec r6 0fh inc r7 1fh dec r7 20h jb bit,rel 30h jnb bit,rel 21h ajmp addr11 31h acall addr11 22h ret 32h reti 23h rl a 33h rlc a 24h add a,#data 34h addc a,#data 25h add a,direct 35h addc a,direct 26h add a,@r0 36h addc a,@r0 27h add a,@r1 37h addc a,@r1 28h add a,r0 38h addc a,r0 29h add a,r1 39h addc a,r1 2ah add a,r2 3ah addc a,r2 2bh add a,r3 3bh addc a,r3 2ch add a,r4 3ch addc a,r4 2dh add a,r5 3dh addc a,r5 2eh add a,r6 3eh addc a,r6 2fh add a,r7 3fh addc a,r7 note: *the a5h opcode is used as a trap instruction for the implementation of software breakpoints.
instruction set 42 revision 2 40h jc rel 50h jnc rel 41h ajmp addr11 51h acall addr11 42h orl direct,a 52h anl direct,a 43h orl direct,#data 53h anl direct,#data 44h orl a,#data 54h anl a,#data 45h orl a,direct 55h anl a,direct 46h orl a,@r0 56h anl a,@r0 47h orl a,@r1 57h anl a,@r1 48h orl a,r0 58h anl a,r0 49h orl a,r1 59h anl a,r1 4ah orl a,r2 5ah anl a,r2 4bh orl a,r3 5bh anl a,r3 4ch orl a,r4 5ch anl a,r4 4dh orl a,r5 5dh anl a,r5 4eh orl a,r6 5eh anl a,r6 4fh orl a,r7 5fh anl a,r7 60h jz rel 70h jnz rel 61h ajmp addr11 71h acall addr11 62h xrl direct,a 72h orl c,bit 63h xrl direct,#data 73h jmp @a+ dptr 64h xrl a,#data 74h mov a,#data 65h xrl a,direct 75h mov direct,#data 66h xrl a,@r0 76h mov @r0,#data 67h xrl a,@r1 77h mov @r1 68h xrl a,r0 78h mov r0,#data 69h xrl a,r1 79h mov r1,#data 6ah xrl a,r2 7ah mov r2,#data 6bh xrl a,r3 7bh mov r3,#data 6ch xrl a,r4 7ch mov r4,#data 6dh xrl a,r5 7dh mov r5,#data 6eh xrl a,r6 7eh mov r6,#data 6fh xrl a,r7 7fh mov r7,#data table 5-8 ? core8051s instruction set in hexadecimal order (continued) opcode mnemonic opcode mnemonic note: *the a5h opcode is used as a trap instruction for the implementation of software breakpoints.
core8051s v2.4 handbook revision 2 43 80h sjmp rel 90h mov dptr,#data16 81h ajmp addr11 91h acall addr11 82h anl c,bit 92h mov bit,c 83h movc a,@a+ pc 93h movc a,@a+ dptr 84h div ab 94h subb a,#data 85h mov direct,direct 95h subb a,direct 86h mov direct,@r0 96h subb a,@r0 87h mov direct,@r1 97h subb a,@r1 88h mov direct,r0 98h subb a,r0 89h mov direct,r1 99h subb a,r1 8ah mov direct,r2 9ah subb a,r2 8bh mov direct,r3 9bh subb a,r3 8ch mov direct,r4 9ch subb a,r4 8dh mov direct,r5 9dh subb a,r5 8eh mov direct,r6 9eh subb a,r6 8fh mov direct,r7 9fh subb a,r7 a0h orl c,~bit b0h anl c,~bit a1h ajmp addr11 b1h acall addr11 a2h mov c,bit b2h cpl bit a3h inc dptr b3h cpl c a4h mul ab b4h cjne a,#data,rel a5h* ? b5h cjne a,direct,rel a6h mov @r0,direct b6h cjne @r0,#data,rel a7h mov @r1,direct b7h cjne @r1,#data,rel a8h mov r0,direct b8h cjne r0,#data,rel a9h mov r1,direct b9h cjne r1,#data,rel aah mov r2,direct bah cjne r2,#data,rel abh mov r3,direct bbh cjne r3,#data,rel ach mov r4,direct bch cjne r4,#data,rel adh mov r5,direct bdh cjne r5,#data,rel aeh mov r6,direct beh cjne r6,#data,rel afh mov r7,direct bfh cjne r7,#data,rel table 5-8 ? core8051s instruction set in hexadecimal order (continued) opcode mnemonic opcode mnemonic note: *the a5h opcode is used as a trap instruction for the implementation of software breakpoints.
instruction set 44 revision 2 c0h push direct d0h pop direct c1h ajmp addr11 d1h acall addr11 c2h clr bit d2h setb bit c3h clr c d3h setb c c4h swap a d4h da a c5h xch a,direct d5h djnx direct,rel c6h xch a,@r0 d6h xchd a,@r0 c7h xch a,@r1 d7h xchd a,@r1 c8h xch a,r0 d8h djnz r0,rel c9h xch a,r1 d9h djnz r1,rel cah xch a,r2 dah djnz r2,rel cbh xch a,r3 dbh djnz r3,rel cch xch a,r4 dch djnz r4,rel cdh xch a,r5 ddh djnz r5,rel ceh xch a,r6 deh djnz r6,rel cfh xch a,r7 dfh djnz r7,rel e0h movx a,@dptr f0h movx@dptr,a e1h ajmp addr11 f1h acall addr11 e2h movx a,@r0 f2h movx@r0,a e3h movx a,@r1 f3h movx@r1,a e4h clr a f4h cpl a e5h mov a,direct f5h mov direct,a e6h mov a,@r0 f6h mov@r0,a e7h mov a,@r1 f7h mov@r1,a e8h mov a,r0 f8h mov r0,a e9h mov a,r1 f9h mov r1,a eah mov a,r2 fah mov r2,a ebh mov a,r3 fbh mov r3,a ech mov a,r4 fch mov r4,a edh mov a,r5 fdh mov r5,a eeh mov a,r6 feh mov r6,a efh mov a,r7 ffh mov r7,a table 5-8 ? core8051s instruction set in hexadecimal order (continued) opcode mnemonic opcode mnemonic note: *the a5h opcode is used as a trap instruction for the implementation of software breakpoints.
core8051s v2.4 handbook revision 2 45 instruction definitions all core8051s core instructions can be condens ed to 53 basic operations, alphabetically ordered according to the operation mnemonic section, as shown in ta b l e 5 - 9 . table 5-9 ? psw flag modificati on (cy, ov, ac) instruction flag instruction flag cy ov ac cy ov ac add xxx setb c 1?? addc xxx clr c 0?? subb xxx cpl c x?? mul 0x? anl c,bit x?? div 0x? anl c,~bit x?? da x?? orl c,bit x?? rrc x?? orl c,~bit x?? rlc x?? mov c,bit x?? cjne x?? note: in this table, ?x? denotes that the indicated flag is affected by the instruction and can be a logic 1 or logic 0, depending upon specific calcul ations. if a particular box is blank, that flag is unaffected by the listed instruction.
instruction set 46 revision 2 c compiler support because the core8051s is 100% compatible with the asm51 instruction set and supports the three traditional 8051 microcontroller memory spaces, it may be targeted by existing 8051 c compilers. the following section describes in more detail the considerations involved in writing c code for the 8051, when using the keil cx51 c compiler. note that the considerations are similar to those required for other 8051 c compilers, such as the small device c compiler (sdcc), which is bundled with actel's softconsole software development environment. ansi c compliance it is theoretically possible to writ e fully compliant ansi c code and target it to the core8051s. however, there are a number of issues to be aware of, as listed below. ? some of the types for the arguments of functions in the keil c runtime library are modified from those defined in the standard ansi c. this is to use smaller sizes, where possible. ? some of the functions in the ke il c runtime library use proprietary extensions to c (as described in "allocation of variables in c" ), such as bit and xdata types. ? some of the functions defined by ansi c ar e not present in the keil c runtime library. ? the keil c runtime library contains some extra functions not defined in ansi c. therefore, pure standard ansi c c ode is guaranteed to run only if it does not use any of the above functions when using the keil c runtime library. alte rnatively, the user may pr ovide a runtime library other than the keil c runtime library. to get optimal usage of the 8051 architecture, how ever, many users would just modify their ansi c application, if necessary, to make op timal use of the 8051 architecture. allocation of variables in c one of the considerations in writing c software for an 8051-based system is allocation of variables. specifically, from which of the three memory spaces is a particular variable allocated? by default, if no c extensions are used, all variable s are allocated from a single memo ry space, therefore allowing no confusion. the keil c compiler allows the user to select a ?memory model? from one of three possible models. these are the small, compact, and large m odels. the small and large models are of particular interest in targeting the core8051s. thes e are described in the following sections. small model in this model, all variables, by default, reside in internal data memory. in this model, variable access is very efficient. however, all objects (if not explicitly located in another memory area) and the stack must fit into internal ram. stack size is critical becaus e the stack size depends on the nesting depth of the various functions. large model in the large model, all variables, by default, reside in external data memory (which may be up to 64 kbytes). in the case of core8051s, this covers 60 kbytes of external ram and 4 kbytes of memory- mapped peripherals. the data pointer (dptr) is used to address external memory, which results in slower accesses to variables than in the small model. it is likely, however, that the large model is the more appropriate of the two for targeting core8051s without having to use language extensions, as this allows the peripheral resources to be mapped as c variables. proprietary extensio ns to c for 8051 as mentioned above, the user may decide to write the application in portable ansi c. however, many users will make use of nonstandard extensions prov ided by the various c compilers, to make more optimal use of the 8051 architecture . in particular, the features of the 8051 architecture that are of
core8051s v2.4 handbook revision 2 47 interest are the address/data path widths as well as the different memory spaces. c compilers for the 8051 provide some extensions to c, which allow more efficient use of the 8051 memory spaces. memory types different memory types are specified. for example, table 5-10 summarizes some of the memory type specifiers, which may be used with the keil cx51 compiler. as with signed and unsigned attributes, the memory type specifiers may be included in the variable declaration. for example: char data var1; char code text[] = ?enter parameter:?; unsigned long xdata array[100]; float idata x,y,z; unsigned char xdata vector[10][4][4]; char bdata flags; if no memory type is specified for a variable, the co mpiler implicitly locates the variable in the default memory space determined by the memory model: small or large . function arguments and automatic variables that cannot be located in regist ers are also stored in the default memory area. data types as well as the standard data types, 8051 c compile rs also define specific data types, which may be used in the c code. for example, the keil cx51 comp iler specifies the additional data types shown in table 5-11 . note that data types relate to the sizes of the stand ard data types, as implemented by c compilers for the 8051. the following sizes are used: table 5-10 ? memory type specifiers for keil cx51 compiler memory type description code program memory (64 kbytes); accessed by opcode movc @a + dptr. data directly addressable internal data memory. this gives the fastest access to variables (128 bytes). idata indirectly addressable internal data memory. variables with this type may be accessed across the full internal address space (256 bytes). bdata bit-addressable internal data memory. this supports mixed bit and byte access. xdata external data memory (64 kbytes). this is accessed by opcode movx @dptr. table 5-11 ? cx51 additional data types data types bits bytes value range bit 1 0 or 1 sbit 1 0 or 1 sfr 8 1 0 to 255 sfr16 16 2 0 to 65535 table 5-12 ? size of standard c data types for 8051 compilers data type size (bits) char 8 int 16 long 32
instruction set 48 revision 2 pointers because of the unique nature of the 8051 architec ture, management of variable pointers becomes an issue. for example, the address of a variable in intern al data memory is 8 bits and so a pointer to a variable in this space is 8 bits. similarly, a pointer to a variable in external data or program memory is 16 bits wide. memory-specific pointers memory-specific pointers always incl ude a memory type specification in the pointer declaration and always refer to a specific memory area. for example: char data *str; /* ptr to string in data */ int xdata *numtab; /* ptr to int(s) in xdata */ long code *powtab; /* ptr to long(s) in code */ memory-specific pointers can be stored using only o ne byte (idata, data, bdata pointers) or two bytes (code and xdata pointers). generic pointers the keil cx51 compiler allows the use of generic poi nters. generic pointers are declared like standard c pointers. for example: char *s; /* string ptr */ int *numptr; /* int ptr */ generic pointers are always stored using three bytes. th e first byte is the memory type, the second is the high-order byte of the offset, and the third is the lo w-order byte of the offset. generic pointers may be used to access any variable, regard less of its location in 8051 memory space. code t hat uses generic pointers runs more slowly and is larger due to the co nversion required and the need to link in other library routines. however, it is worthwhile if there is a n eed to mix different memory spaces. an example is the case where a display function is required to acc ept pointers to code for fixed message prompts and pointers to xdata for messages put together by softwa re during execution. if a message stored in code space is passed to a display function that uses xdata space, the result is garbage. in summary, by selecting a specific memory model and by the use of generic pointers and a modified runtime library, it is possible for a programmer to use ansi c to target an 8051 derivative, such as core8051s. to achieve better syst em performance and smaller code size, however, the user may utilize language extensions specified by the c compiler. c header files reg51.h a customized version of the reg51.h file is required when compiling c code for core8051s. this contains the following:" /*-------------------------------------------------------------------------- reg51.h header file for actel core8051s microcontroller. copyright (c) actel corporation 2006. all rights reserved. --------------------------------------------------------------------------*/ #ifndef __reg51_h__ #define __reg51_h__ float 32 double 64 table 5-12 ? size of standard c data types for 8051 compilers
core8051s v2.4 handbook revision 2 49 /* byte registers */ sfr sp = 0x81; sfr dpl = 0x82; sfr dph = 0x83; sfr dpl1 = 0x84; sfr dph1 = 0x85; sfr icon = 0x88; sfr dps = 0x92; sfr xwb1 = 0x9a; sfr xwb2 = 0x9b; sfr xwb3 = 0x9c; sfr xrb1 = 0x9d; sfr xrb2 = 0x9e; sfr xrb3 = 0x9f; sfr ie = 0xa8; sfr psw = 0xd0; sfr acc = 0xe0; sfr b = 0xf0; /* bit register */ /* psw */ sbit cy = 0xd7; sbit ac = 0xd6; sbit f0 = 0xd5; sbit rs1 = 0xd4; sbit rs0 = 0xd3; sbit ov = 0xd2; sbit p = 0xd0; #endif " stdio.h core8051s requires a custom-designed stdio library, as it doesn't contain the serial channel normally found in 8051-based microcontrollers.

revision 2 51 6 ? instruction timing program memory bus cycle the execution for instruction n is performed during the fetch of instruction n + 1. a program memory fetch cycle without wait states is shown in figure 6-1 . a program memory fetch cycle with wait states is shown in figure 6-2 on page 52 . a program memory read cycle without wait states is shown in figure 6-3 on page 52 . a program memory read cycle wit h wait states is shown in figure 6-4 on page 53 . figure 6-1 through to figure 6-12 on page 57 have been taken from the core8051 datasheet . the following conventions are used in figure 6-1 to figure 6-14 on page 57 . table 6-1 ? conventions used in figure 18 to figure 31 convention description tclk time period of clk signal n address of actually executed instruction (n) instruction fetched from address n n+1 address of next instruction addr address of memory cell data data read from address addrl read sample point of reading the data fr om the bus into the internal register write sample point of writing the data from the bus into memory ramcs off-core signal is made on the base ramwe and clk signals figure 6-1 ? program memory fetch cy cle without wait states 0 ns 50 ns 150 ns 200 ns 250 ns 300 ns 100 ns clk memaddr memrd memwr mempsrd mempswr mempsack memdatao n n + 1 n + 2 memdatai read sample (n) (n + 2) (n + 1) read sample read sample sample sample sample
instruction timing 52 revision 2 figure 6-2 ? program memory fetch cycle with wait states figure 6-3 ? program memory read cycle without wait states 0 ns 50 ns 150 ns 200 ns 250 ns 300 ns 100 ns clk memaddr memrd memwr mempsrd mempswr mempsack memdatao n n + 1 n + 2 sample memdatai read sample read sample (n) (n + 1) read sample sample sample sample sample 0 ns 50 ns 150 ns 200 ns 250 ns 100 ns clk memaddr memrd memwr mempsrd mempswr mempsack memdatao n n + 1 addr memdatai read sample read sample (n) (n + 1) read sample sample sample sample 300 ns 350 ns n + 1 data
core8051s v2.4 handbook revision 2 53 external data memory bus cycle example bus cycles for external data memory access are shown in figure 6-5 through figure 6-12 on page 57 . figure 6-5 on page 53 shows an external data memory read cycle without stretch cycles. figure 6-4 ? program memory read cycle with wait states 0 ns 50 ns 150 ns 200 ns 250 ns 300 ns 100 ns clk memaddr memrd memwr mempsrd mempswr mempsack memdatao n n + 1 addr sample memdatai read sample read sample (n) (n + 1) read sample sample sample sample sample 350 ns n + 1 data sample figure 6-5 ? external data memory read cycle without stretch cycles 0 ns 50 ns 150 ns 200 ns 250 ns 100 ns clk memaddr memrd memwr mempsrd memdatao n n + 1 n + 1 memdatai read sample read sample (n) (n + 1) read sample max. 1 tclk addr data
instruction timing 54 revision 2 figure 6-6 ? external data memory read cycle with one stretch cycle figure 6-7 ? external data memory read with two stretch cycles 0 ns 50 ns 150 ns 200 ns 250 ns 300 ns 100 ns clk memaddr memrd memwr mempsrd mempswr mempsack memdatao n n + 1 n + 1 sample memdatai read sample read sample (n) (n + 1) read sample sample sample sample sample 350 ns addr sample data 0 ns 50 ns 150 ns 200 ns 250 ns 100 ns clk memaddr memrd memwr mempsrd memdatao n n + 1 n + 1 memdatai read sample read sample (n) (n + 1) read sample max. 3 tclk addr data
core8051s v2.4 handbook revision 2 55 figure 6-8 ? external data memory read cycle with seven stretch cycles figure 6-9 ? external data memory write cycle without stretch cycles 0 ns 100 ns 300 ns 400 ns 200 ns clk memaddr memrd memwr mempsrd memdatao n + 1 memdatai max. 8 tclk (n) (n + 1) addr data n + 1 n read sample read sample read sample 50 ns 150 ns 350 ns 450 ns 250 ns 0 ns 50 ns 150 ns 200 ns 100 ns clk memaddr memrd memwr mempsrd memdatao n + 1 memdatai read sample write sample (n) addr data 250 ns read sample n + 1 n (n + 1)
instruction timing 56 revision 2 figure 6-10 ? external data memory write cycle with one stretch cycle figure 6-11 ? external data memory write cycle with two stretch cycles 0 ns 50 ns 150 ns 200 ns 250 ns 100 ns clk memaddr memrd memwr mempsrd memdatao n + 1 memdatai read sample write sample (n) (n + 1) addr data read sample n + 1 n 0 ns 100 ns 300 ns 200 ns clk memaddr memrd memwr mempsrd memdatao n + 1 memdatai read sample write sample (n) (n + 1) addr data read sample n + 1 50 ns 150 ns 350 ns 250 ns
core8051s v2.4 handbook revision 2 57 apb bus cycles example bus cycles for apb bus cycles are shown in figure 6-13 and figure 6-14 . figure 6-12 ? external data memory write cycle with seven stretch cycles 0 ns 100 ns 300 ns 400 ns 500 ns 200 ns clk memaddr memrd memwr mempsrd memdatao n + 1 memdatai read sample write sample (n) (n + 1) addr data read sample figure 6-13 ? apb write transfer bus cycle figure 6-14 ? apb read transfer bus cycle 0 ns 50 ns 150 ns 200 ns 250 ns 300 ns 100 ns 350 ns 400 ns clk0 paddr pwrite psel penable pwdata addr 1 data 1 0 ns 50 ns 150 ns 200 ns 250 ns 300 ns 100 ns 350 ns 400 ns pclk paddr pwrite psel penable prdata addr 1 data 1

revision 2 59 7 ? list of changes list of changes the following table lists critical changes that were made in each revision of the handbook date changes page august 2010 the core version was updated to v2.4 n/a type was changed from input to output for the memdatao signal in ta b l e 2 - 1 ? core8051s ports . 18 the "optional registers and instructions" section was updated to state that the behavior of the processor is undefined when attempting to execute a mul, div or da instruction while the processor is no t configured to include support for these instructions. 22 the name of the interrupt enable register was changed from ien to ie in ta b l e 4 - 1 ? core8051s sfr registers , the "interrupt enable register (ie)" section , and the "interrupts" section . 31 , 33 , 34 the "interrupt control register (icon)" section was revised to state that the icon register implements a subset of the timer control (tcon) register. 33 in table 5-8 ? core8051s instruction set in hexadecimal order , the opcode "a5h*" was corrected. it had previously been listed as "ash." the "b5h" opcode was corrected from "bsh." a footnote was added to the table stating that the a5h opcode is used as a trap instruction for the implementat ion of software breakpoints. 41 , 43 the "c compiler support" section was modified by adding the statement that the small device c compiler (sdcc) is bundled with actel's softconsole software development environment. 46

revision 2 61 a ? product support actel backs its products with various support services includi ng customer service, a customer technical support center, a web site, an ftp site, electronic mail, and worldwide sales offices. this appendix contains information about contacting actel and using these support services. customer service contact customer service for non-technical product su pport, such as product pricing, product upgrades, update information, order st atus, and authorization. from northeast and north central u.s.a., call 650.318.4480 from southeast and s outhwest u.s.a., call 650. 318.4480 from south central u.s.a., call 650.318.4434 from northwest u.s.a., call 650.318.4434 from canada, call 650.318.4480 from europe, call 650.318.4252 or +44 (0) 1276 401 500 from japan, call 650.318.4743 from the rest of the world, call 650.318.4743 fax, from anywhere in the world 650.318.8044 actel customer technical support center actel staffs its customer technical support center with highly skilled engineers who can help answer your hardware, software, and design questions. the customer technical support center spends a great deal of time creating application notes and answers to faqs. so, before you contact us, please visit our online resources. it is very likely we have already answered your questions. actel technical support visit the actel customer support website ( www.actel.com/support/search/default.aspx ) for more information and support. many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the actel web site. website you can browse a variety of technical and non -technical information on actel?s home page, at www.actel.com . contacting the customer technical support center highly skilled engineers staff the technical support c enter from 7:00 a.m. to 6:00 p.m., pacific time, monday through friday. several ways of contacting the center follow: email you can communicate your technical questions to ou r email address and receive answers back by email, fax, or phone. also, if you have design problems, y ou can email your design files to receive assistance. we constantly monitor the email account throughout the day. when sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request.
product support 62 revision 2 the technical support email address is tech@actel.com . phone our technical support center answers all calls. th e center retrieves informa tion, such as your name, company name, phone number and your question, and then issues a case number. the center then forwards the information to a queue where the first available application engineer receives the data and returns your call. the phone hours are from 7:00 a.m. to 6:00 p.m., pacific time, monday through friday. the technical support numbers are: 650.318.4460 800.262.1060 customers needing assistance outside the us time zones can either contact technical support via email (tech@actel.com) or contact a local sales office. sales office listings can be found on the website at www.actel.com/company/contact/default.aspx .
revision 2 63 index a actel electronic mail 61 telephone 62 web-based technical support 61 website 61 c c header files 48 contacting actel customer service 61 electronic mail 61 telephone 62 web-based technical support 61 customer service 61 e external data memory space 30 g generics 20 i instruction definitions 45 instruction set 35 instruction timing 51 internal data memory space 31 m microcontroller features 5 o overview 15 p parameters 20 port signals 17 ports 17 product support 62 customer service 61 electronic mail 61 technical support 61 telephone 62 website 61 program memory 29 s sfr registers 31 software memory map 29 speed advantage summary 15 t technical support 61 w web-based technical support 61
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